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august 2012 fdmc7208s dual n-channel powertrench ? mosfet ?2012 fairchild semiconductor corporation 1 www.fairchildsemi.com fdmc7208s rev.c2 fdmc7208s dual n-channel powertrench ? mosfet q1: 30 v, 12 a, 9.0 m q2: 30 v, 16 a, 6.4 m features q1: n-channel ? max r ds(on) = 9.0 m at v gs = 10 v, i d = 12 a ? max r ds(on) = 11.0 m at v gs = 4.5 v, i d = 11 a q2: n-channel ? max r ds(on) = 6.4 m at v gs = 10 v, i d = 16 a ? max r ds(on) = 7.5 m at v gs = 4.5 v, i d = 13.5 a ? termination is lead-free and rohs compliant general description this device includes two 30v n-channel mosfets in a dual power 33 (3 mm x 3 mm mlp) package. the package is en- hanced for exceptional thermal performance. applications ? computing ? communications ? general purpose point of load ? notebook system d1 d2 s1 g1 s2 g2 power 33 pin 1 s1 s1 s2 s2 mosfet maximum ratings t a = 25 c unless otherwise noted thermal characteristics package marking and ordering information symbol parameter q1 q2 units v ds drain to source voltage 30 30 v v gs gate to source voltage (note 4) 20 12 v i d drain current -continuous (package limited) t c = 25 c 22 26 a -continuous t a = 25 c 12 1a 16 1b -pulsed 60 80 e as single pulse avalanche energy (note 3) 21 21 mj p d power dissipation for single operation t a = 25 c 1.9 1a 1.9 1b w power dissipation for single operation t a = 25 c 0.8 1c 0.8 1d t j , t stg operating and storage junction temperature range -55 to +150 c r ja thermal resistance, junction to ambient 65 1a 65 1b c/w r ja thermal resistance, junction to ambient 155 1c 155 1d device marking device package reel size tape width quantity fdmc7208s fdmc7208s power 33 13 ? 12 mm 3000 units
fdmc7208s dual n-channel powertrench ? mosfet ?2012 fairchild semiconductor corporation 2 www.fairchildsemi.com fdmc7208s rev.c2 electrical characteristics t j = 25 c unless otherwise noted off characteristics on characteristics dynamic characteristics switching characteristics symbol parameter test conditions type min typ max units bv dss drain to source breakdown voltage i d = 250 a, v gs = 0 v i d = 1 ma, v gs = 0 v q1 q2 30 30 v bv dss t j breakdown voltage temperature coefficient i d = 250 a, referenced to 25 c i d = 10 ma, referenced to 25 c q1 q2 27 21 mv/c i dss zero gate voltage drain current v ds = 24 v, v gs = 0 v q1 q2 1 500 a i gss gate to source leakage current, forward v gs = 20 v, v ds = 0 v v gs = 12 v, v ds = 0 v q1 q2 100 100 na v gs(th) gate to source threshold voltage i d = 250 a, v gs = 0 v i d = 1 ma, v gs = 0 v q1 q2 1.2 1.2 1.7 1.6 3.0 3.0 v v gs(th) t j gate to source threshold voltage temperature coefficient i d = 250 a, referenced to 25 c i d = 10 ma, referenced to 25 c q1 q2 -5 -3 mv/c r ds(on) drain to source on resistance v gs = 10 v, i d = 12 a v gs = 4.5 v, i d = 11 a v gs = 10 v, i d = 12 a, t j = 125 c q1 6.7 8.8 9.2 9.0 11.0 12.4 m v gs = 10 v, i d = 16 a v gs = 4.5 v, i d = 13.5 a v gs = 10 v, i d = 16 a , t j = 125 c q2 4.7 5.3 6.4 6.4 7.5 6.8 g fs forward transconductance v ds = 5 v, i d = 12 a v ds = 5 v, i d = 16 a q1 q2 53 80 s c iss input capacitance q1: v ds = 15 v, v gs = 0 v, f = 1 mhz q2: v ds = 15 v, v gs = 0 v, f = 1 mhz q1 q2 848 1685 1130 2245 pf c oss output capacitance q1 q2 270 432 360 575 pf c rss reverse transfer capacitance q1 q2 36 42 55 65 pf r g gate resistance q1 q2 0.1 0.1 1.1 1.0 2.5 2.5 t d(on) turn-on delay time q1: v dd = 15 v, i d = 12 a, r gen = 6 q2: v dd = 15 v, i d = 16 a, r gen = 6 q1 q2 6 7 12 14 ns t r rise time q1 q2 2 3 10 10 ns t d(off) turn-off delay time q1 q2 16 23 29 36 ns t f fall time q1 q2 2 2 10 10 ns q g total gate charge v gs = 0 v to 10 v q1 v dd = 15 v, i d = 12 a q2 v dd = 15 v, i d = 16 a q1 q2 13 26 18 36 nc q g total gate charge v gs = 0 v to 5 v q1 q2 6.7 14 9.4 20 nc q gs gate to source gate charge q1 q2 2.3 3.9 nc q gd gate to drain ?miller? charge q1 q2 1.8 2.7 nc
fdmc7208s dual n-channel powertrench ? mosfet ?2012 fairchild semiconductor corporation 3 www.fairchildsemi.com fdmc7208s rev.c2 electrical characteristics t j = 25 c unless otherwise noted drain-source diod e characteristics symbol parameter test conditions type min typ max units v sd source to drain diode forward voltage v gs = 0 v, i s = 2 a (note 2) v gs = 0 v, i s = 12 a (note 2) v gs = 0 v, i s = 2 a (note 2) v gs = 0 v, i s = 16 a (note 2) q1 q1 q2 q2 0.72 0.82 0.70 0.82 1.2 1.2 1.2 1.2 v t rr reverse recovery time q1 i f = 12 a, di/dt = 100 a/ s q2 i f = 16 a, di/dt = 300 a/ s q1 q2 21 21 34 33 ns q rr reverse recovery charge q1 q2 6 16 12 28 nc notes: 1.r ja is determined with the device mounted on a 1 in 2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of fr-4 material. r jc is guaranteed by design while r ca is determined by the user's board design. 2. pulse test: pulse width < 300 s, duty cycle < 2.0%. 3. q1: e as of 21 mj is based on starting t j = 25 o c, l = 0.3 mh, i as = 12 a, v dd = 27 v, v gs = 10 v. 100% tested at l = 3 mh, i as = 5.2 a. q1: e as of 21 mj is based on starting t j = 25 o c, l = 0.3 mh, i as = 12 a, v dd = 27 v, v gs = 10 v. 100% tested at l = 3 mh, i as = 5.4 a. 4. as an n-ch device, the negative vgs rating is for low du ty cycle pulse occurrence only. no continuous rating is implied a. 65 c/w when mounted on a 1 in 2 pad of 2 oz copper b. 65 c/w when mounted on a 1 in 2 pad of 2 oz copper g df ds sf ss g df ds sf ss c. 155 c/w when mounted on a minimum pad of 2 oz copper d. 155 c/w when mounted on a minimum pad of 2 oz copper g df ds sf ss g df ds sf ss
fdmc7208s dual n-channel powertrench ? mosfet ?2012 fairchild semiconductor corporation 4 www.fairchildsemi.com fdmc7208s rev.c2 typical characteristics (q1 n-channel) t j = 25c unless otherwise noted figure 1. 012345 0 10 20 30 40 50 60 v gs = 4 v v gs = 3.5 v v gs = 4.5 v pulse duration = 80 p s duty cycle = 0.5% max v gs = 3 v v gs = 10 v i d , drain current (a) v ds , drain to source voltage (v) on region characteristics figure 2. 0 102030405060 0 1 2 3 4 5 v gs = 3.5 v pulse duration = 80 p s duty cycle = 0.5% max normalized drain to source on-resistance i d , drain current (a) v gs = 4 v v gs = 4.5 v v gs = 3 v v gs = 10 v n o r m a l i z e d o n - r e s i s t a n c e vs drain current and gate voltage f i g u r e 3 . n o r m a l i z e d o n r e s i s t a n c e -75 -50 -25 0 25 50 75 100 125 150 0.6 0.8 1.0 1.2 1.4 1.6 i d = 12 a v gs = 10 v normalized drain to source on-resistance t j , junction temperature ( o c ) vs junction temperature figure 4. 2345678910 0 10 20 30 40 t j = 125 o c i d = 12 a t j = 25 o c v gs , gate to source voltage (v) r ds(on) , drain to source on-resistance ( m : ) pulse duration = 80 p s duty cycle = 0.5% max o n - r e s i s t a n c e v s g a t e t o source voltage figure 5. transfer characteristics 1.01.52.02.53.03.54.0 0 10 20 30 40 50 60 t j = 150 o c v ds = 5 v pulse duration = 80 p s duty cycle = 0.5% max t j = -55 o c t j = 25 o c i d , drain current (a) v gs , gate to source voltage (v) figure 6. 0.00.20.40.60.81.01.2 0.001 0.01 0.1 1 10 100 t j = -55 o c t j = 25 o c t j = 150 o c v gs = 0 v i s , reverse drain current (a) v sd , body diode forward voltage (v) s o u r c e t o d r a i n d i o d e forward voltage vs source current
fdmc7208s dual n-channel powertrench ? mosfet ?2012 fairchild semiconductor corporation 5 www.fairchildsemi.com fdmc7208s rev.c2 figure 7. 051 01 5 0 2 4 6 8 10 i d = 12 a v dd = 20 v v dd = 15 v v gs , gate to source voltage (v) q g , gate charge (nc) v dd = 10 v gate charge characteristics figure 8. 0.1 1 10 30 10 100 1000 2000 f = 1 mhz v gs = 0 v capacitance (pf) v ds , drain to source voltage (v) c rss c oss c iss c a p a c i t a n c e v s d r a i n to source voltage figure 9. 0.01 0.1 1 10 100 1 10 40 t j = 100 o c t j = 25 o c t j = 125 o c t av , time in avalanche (ms) i as , avalanche current (a) u n c l a m p e d i n d u c t i v e switching capability figure 10. 0.01 0.1 1 10 100 0.01 0.1 1 10 100 derived from test data 10 s 10 ms dc 1 s 100 ms 1 ms i d , drain current (a) v ds , drain to source voltage (v) this area is limited by r ds(on) single pulse t j = max rated r t ja = 155 o c/w t a = 25 o c f o r w a r d b i a s s a f e operating area figure 11. single pulse maximum power dissipa tion 10 -3 10 -2 10 -1 10 0 10 1 100 1000 0.5 1 10 100100 p (pk) , peak transient power (w) single pulse r t ja = 155 o c/w t a = 25 o c t, pulse width (sec) typical characteristics (q1 n-channel) t j = 25c unless otherwise noted
fdmc7208s dual n-channel powertrench ? mosfet ?2012 fairchild semiconductor corporation 6 www.fairchildsemi.com fdmc7208s rev.c2 figure 12. junction-to-ambient transient thermal response curve 10 -3 10 -2 10 -1 10 0 10 1 100 1000 0.005 0.01 0.1 1 single pulse r t ja = 155 o c/w (note 1b) duty cycle-descending order normalized thermal impedance, z t ja t, rectangular pulse duration (sec) d = 0.5 0.2 0.1 0.05 0.02 0.01 2 p dm t 1 t 2 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z t jc x r t jc + t c typical characteristics (q1 n-channel) t j = 25c unless otherwise noted
fdmc7208s dual n-channel powertrench ? mosfet ?2012 fairchild semiconductor corporation 7 www.fairchildsemi.com fdmc7208s rev.c2 typical characteristics (q2 n-channel) t j = 25 c unless otherwise noted figure 14. on- region characteristics figure 15. normalized on-resistance vs drain current and gate voltage figure 16. normalized on-resistance vs junction temperature figure 17. on-resistance vs gate to source voltage figure 18. transfer characteristics figure 19. source to drain diode forward voltage vs source current 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 20 40 60 80 v gs = 4 v v gs = 3.5 v v gs = 4.5 v pulse duration = 80 s duty cycle = 0.5% max v gs = 3 v v gs = 10 v i d , drain current (a) v ds , drain to source voltage (v) 0 20406080 0 1 2 3 4 5 v gs = 3.5 v pulse duration = 80 s duty cycle = 0.5% max normalized drain to source on-resistance i d , drain current (a) v gs = 4 v v gs = 4.5 v v gs = 3 v v gs = 10 v -75 -50 -25 0 25 50 75 100 125 150 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 i d = 16 a v gs = 10 v normalized drain to source on-resistance t j , junction temperature ( o c ) 246810 0 6 12 18 24 30 t j = 125 o c i d = 16 a t j = 25 o c v gs , gate to source voltage (v) r ds(on) , drain to source on-resistance ( m ) pulse duration = 80 s duty cycle = 0.5% max 1234 0 16 32 48 64 80 t j = 125 o c v ds = 5 v pulse duration = 80 s duty cycle = 0.5% max t j = -55 o c t j = 25 o c i d , drain current (a) v gs , gate to source voltage (v) 0.00.20.40.60.81.01.2 0.001 0.01 0.1 1 10 100 t j = -55 o c t j = 25 o c t j = 125 o c v gs = 0 v i s , reverse drain current (a) v sd , body diode forward voltage (v)
fdmc7208s dual n-channel powertrench ? mosfet ?2012 fairchild semiconductor corporation 8 www.fairchildsemi.com fdmc7208s rev.c2 typical characteristi cs (q2 n-channel) t j = 25c unless otherwise noted figure 20. gate charge characteristics figure 21. capacitance vs drain to source voltage figure 22. unclamped inductive switching capability f i g u r e 2 3 . f o r w a r d b i a s s a f e operating area figure 24. single pulse maximum power dissipation 0 6 12 18 24 30 0 2 4 6 8 10 i d = 16 a v dd = 20 v v dd = 15 v v gs , gate to source voltage (v) q g , gate charge (nc) v dd = 10 v 0.1 1 10 30 10 100 1000 3000 f = 1 mhz v gs = 0 v capacitance (pf) v ds , drain to source voltage (v) c rss c oss c iss 0.001 0.01 0.1 1 10 100 1 10 40 t j = 100 o c t j = 25 o c t j = 125 o c t av , time in avalanche (ms) i as , avalanche current (a) 0.01 0.1 1 10 100 0.01 0.1 1 10 100 derived from test data 10 s 10 ms dc 1 s 100 ms 1 ms i d , drain current (a) v ds , drain to source voltage (v) this area is limited by r ds(on) single pulse t j = max rated r ja = 155 o c/w t a = 25 o c 10 -3 10 -2 10 -1 10 0 10 1 100 1000 0.5 1 10 100 100 p (pk) , peak transient power (w) single pulse r ja = 155 o c/w t a = 25 o c t, pulse width (sec)
typical characteristics (q2 n-channel) t j = 25 c unless otherwise noted figure 26. junction-to-ambient transient thermal response curve 10 -3 10 -2 10 -1 10 0 10 1 100 1000 0.005 0.01 0.1 1 single pulse r t ja = 155 o c/w (note 1b) duty cycle-descending order normalized thermal impedance, z t ja t, rectangular pulse duration (sec) d = 0.5 0.2 0.1 0.05 0.02 0.01 2 p dm t 1 t 2 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z t jc x r t jc + t c fdmc7208s dual n-channel powertrench ? mosfet ?2012 fairchild semiconductor corporation 9 www.fairchildsemi.com fdmc7208s rev.c2
fdmc7208s dual n-channel powertrench ? mosfet ?2012 fairchild semiconductor corporation 10 www.fairchildsemi.com fdmc7208s rev.c2 syncfet tm schottky body diode characteristics fairchild?s syncfet tm process embeds a schottky diode in parallel with powertrench mosfet . this diode exhibits similar characteristics to a discrete exte rnal schottky diode in parallel with a mosfet. figure 27 shows the reverses recovery characteristic of the fdmc7208s. schottky barrier diodes exhibit significant leakage at high tem- perature and high reverse voltage. this will increase the power in the device. figure 27. fdmc7208s syncfet tm body diode reverse recovery characteristic 0 40 80 120 160 200 -5 0 5 10 15 20 current (a) time (ns) figure 28. syncfet tm body diode reverses leakage versus drain-source voltage 0 5 10 15 20 25 30 10 -7 10 -6 10 -5 10 -4 10 -3 10 -2 t j = 125 o c t j = 100 o c t j = 25 o c i dss , reverse leakage current (a) v ds , reverse voltage (v) typical characteristics (continued)
fdmc7208s dual n-channel powertrench ? mosfet ?2012 fairchild semiconductor corporation 11 www.fairchildsemi.com fdmc7208s rev.c2 dimensional outline and pad layout
fdmc7208s dual n-channel powertrench ? mosfet ?2012 fairchild semiconductor corporation 12 www.fairchildsemi.com fdmc7208s rev.c2 trademarks the following includes registered and unregistered trademarks and se rvice marks, owned by fairchild semiconductor and/or its gl obal subsidiaries, and is not intended to be an exhaustive list of all such trademarks. *trademarks of system general corporation, used under license by fairchild semiconductor. disclaimer fairchild semiconductor reserves the right to make changes wi thout further notice to any products herein to improve reliability, function, or design. fairchild does not assume an y liability arising out of the application or use of any product or circuit described herein; neither does it convey an y license under its patent rights, nor the rights of others. these specifications do not expand the terms of fairchild?s wo rldwide terms and conditions, specifically the warranty therein, which covers these products. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fai rchild semiconductor corporation. as used here in: 1. life support devices or systems ar e devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform c an be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms 2cool? 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